Texas Instruments OMAP5912 Reference Manual page 841

Memory Interfaces for the EMIFS
2.1.10 Error Code Correction
To better protect data, the NFC provides an error code correction (ECC) logic.
The algorithm for ECC is the one that Samsung recommends (see Figure 10).
It can be used on 256 bytes or 512 bytes (selectable by a control bit in the
NND_CTRL register), and can detect errors and correct one bit error. The ECC
logic can be used either for read or program operation.
Bit checking and eventual bit repair is done by software after either half-page
or page read.
When program operation is used, ECC is normally accumulated. It is the
responsibility of the software to read the ECC through dedicated registers
(NND_ECCx) via host access and to write them back to the NFMC in the spare
area.
For read operation, the ECC is accumulated after each data read. At least a
half-page needs to be accessed, and the starting address is the beginning of
the half-page. The calculated ECC can be compared with the one that was
previously stored in the spare area when the last program operation in that
page was performed. The NFC does not assume the physical address of the
ECC bytes in the spare byte area.
ECC can be disabled by resetting a bit in the control register (NND_CTRL) of
the NFC.
ECC registers are reset when the RESETN pin at the NFC boundary goes low
or by writing a bit in the NND_RESET register. The management of the ECC
pointer is done automatically by hardware. After a reset, the pointer is set to
register 1 (NND_ECC1). Then, when the number of read/writes exceeds the
ECC length coded by ECC_256 in the NND_CTRL register of the NFC, the
pointer shifts to register 2 (NND_ECC2), next to register 3, and then moves
back to the NND_ECC1 register. During ECC computation, if bit ECC_ON is
reset, the ECC registers are not updated anymore. When ECC_ON is set to
1, the computation resumes. After a write in the NND_RESET register, the
pointer for the ECC is set to NND_ECC1.
SPRU756A Memory Interfaces 35