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Table 9.
Watchdog Control Register (WCLR)
Bit
Name
31:6
RESERVED
5
PRE
4:2
PTV
0:1
RESERVED
Table 10. Watchdog Counter Register (WCRR)
Bit
Name
31:0
TIME_COUNTER
SPRU759B
Base Address = 0xFFFE B000, Offset = 0x24
Function
Reserved
0: The timer clock input pin clocks the counter.
1: The divided input pin clocks the counter.
Prescaler ratio value:
Reserved
This 32-bit register is accessible in 16-bit mode.
Base Address = 0xFFFE B000, Offset = 0x28
Function
Value of timer counter
This 32-bit register is accessible in 16-bit mode.
The WCRR register is a 32-bit register (16-bit addressable). The MPU can
perform either a 32-bit access or two 16-bit accesses to the register, whereas
the DSP performs two consecutive 16-bit transactions. Because the interface
clock is completely asynchronous with the timer clock, some synchronization
is done to ensure that the WCRR value is not read while it is incremented.
In 16-bit-mode, the following sequence must be followed to read the WCRR
register properly:
1) Read the lower 16 bits of the WCRR register (offset = 0x08). When the
WCRR is read, the lower 16 bits (LSBs) are read, and the upper 16 bits
(MSW) of the WCRR register are stored in a temporary register (shadow
register).
2) Read the upper 16 bits of the WCRR register (offset = 0x0A). The value
of the upper 16 bits (MSW), which has been stored in the temporary
register, is read.
To read the value of WCRR correctly, the first OCP read access must be to the
lower 16-bits (that is, offset = 0x08), followed by OCP read access to the upper
16-bits (that is, offset = 0x0A).
WCRR value can be modified by writing on WCRR register and only if
watchdog has been disabled (using WSPR register).
32-Bit Watchdog Timer General Overview
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0x00000
1
0x0
0x0
Reset
0xFFF0 0000
Timers
17
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