Texas Instruments OMAP5912 Reference Manual page 145

Traffic Controller
The DLL behavior can be monitored by the software using the EMIFF DLL
status registers (URD status and WRD status registers). For each DLL, the
current counter value is available (DLLCount field), as well as two status bits:
overflow and underflow. Overflow is set when the DLL counter value is 255
during at least one TC clock cycle, and underflow is set when the DLL counter
is 0 during at least one TC clock cycle.
These two status bits are both reset if the DLL is disabled (ENADLL is set to
0 in the DLL control register).
3.3.9 Page-Closing Strategy
The SDRAM operation register that selects between SDR and DDR also
allows selection of a page-closing strategy. Three variants are available:
SPRU749A OMAP3.2 Subsystem 87