Texas Instruments OMAP5912 Reference Manual page 999

On-Chip/Off-Chip Memory and Peripheral Access Latencies
Table 16. Peripheral Access Time Calculations (Continued)
OCP-T2 Peripherals
MPU to SSR Read
MPU to SST Write
OCP-I Interconnect
MPU to GDD Read/write
MPU Public Peripheral
MPU to Read/write
UART
GDD Accesses
GDD access DMA request
to SSR to read/write
GDD access DMA request
to SST to read/write
GDD access Request to
to SDRAM acknowledge
read/write
MPU Private Peripherals
MPU access Read/write
to level1 int
handler
register
† This latency value includes the following:
− Initial latency: from enable to 1st transaction
− Pipeline latency: from source to destination
− Close latency: from last acknowledge to release of the channel
− For the normal and dedicated P-channel case
‡ Page open: external SDRAM is a mobile DDR
§ 51 equivalent TC cycles = 19 TC cycles plus 16 CCP interface cycles
48 Peripheral Interconnects
Burst Read
Line
Fill
First Data
ns initiato ns
r
cycles
† ‡ †
175 /200 17.5 / 145
‡
20 170
Single Read
initiator ns
cycles
155
70
135
125
† † †
/ 14.5 / 140 /
‡ ‡ ‡
17 130
80
Single Write
initiato ns initiator
r cycles
cycles
31
110 22
14 70 14
27 155 31
12.5
50 5
† † † ‡
14 / 110 / 11 /10
‡ ‡
13 100
16 100 20
SPRU758A