Texas Instruments OMAP5912 Reference Manual page 257

Multimedia processor device overview and architecture
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Table 118. TIPB Control Register (RHEA_CNTL) (Continued)
Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x00
Bit
Name
3:0
ACCESS_FACTOR0
Table 119. TIPB Allocation Control Register (RHEA_BUS_ALLOC)
Base Address = 0xFFFE D300 (Public), 0xFFFE CA00 (Private), Offset = 0x04
Bit
Name
15:6
Reserved
5
EXTNINT_PRIORITY
SPRU749A
Function
Clock period multiplication factor for TIPB strobe 0.
Allows access to slow peripherals by lengthening TIPB
strobe 0 period by a multiple of the internal TIPB bridge
clock period. Note that the TIPB bridge clock period is the
same as the OMAP traffic controller clock period.
0000: Same as 0001.
0001: Strobe period = TIPB bridge clock period x 2
0010: Strobe period = TIPB bridge clock period x 4
0011: Strobe period = TIPB bridge clock period x 6
0100: Strobe period = TIPB bridge clock period x 8
0101: Strobe period = TIPB bridge clock period x 10
0110: Strobe period = TIPB bridge clock period x 12
0111: Strobe period = TIPB bridge clock period x 14
1000: Strobe period = TIPB bridge clock period x
1001: Strobe period = TIPB bridge clock period x 18
1010: Strobe period = TIPB bridge clock period x 20
1011: Strobe period = TIPB bridge clock period x 22
1100: Strobe period = TIPB bridge clock period x 24
1101: Strobe period = TIPB bridge clock period x 26
1110: Strobe period = TIPB bridge clock period x 28
1111: Strobe period = TIPB bridge clock period x 30
Function
Priority between DMA and OCP-I when fixed priority
scheme is selected.
0: DMA has priority.
1: OCP-I has priority.
TIPB Bridge
R/W
R/W
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
0x1
Reset
0x000
0
199

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