Table of Contents
Advertisement
3.4.1
Address and Command Fault Registers
3.4.2
Abort Type Register
3.4.3
Protection Register
3.5
Traffic Controller Registers
SPRU749A
If OS protection is needed, it is recommended that any device integrating the
OMAP 3.2 core provide an MMU or a translation table controlled by the OMAP
MPU. Then it is the responsibility of the system software to ensure that
undefined or unauthorized locations are not accessed.
An internal address checker continuously compares the OCP address bus and
the OMAP 3.2 memory map. An abort signal is provided if the transaction is
not correct.
OCPI contains other status and control registers listed in Table 7, OCP-I
Registers.
When a non-OMAP-defined address is detected or a bus error occurs from the
subtargets on a write access, an abort is sent to the initiator to indicate that the
current access can not be completed. The access to the OMAP subtarget is
terminated and the address and command buses are stored in the fault
registers.
The type of the abort event is reported in a status register.
The interrupt handler can clear this register and the interrupt request by
reading any value to this register.
This register provides access protection to the following targets:
-
EMIF-slow and EMIF-fast
-
OCPT1 and OCPT2
-
Multibank OCPT1/2
-
MPUI
-
MPU private TIPB bridge and MPU public TIPB bridge
The reset value of the protection register bits is determined by the value of the
static_reset_protect_mode pin.
TC registers are distributed into the traffic controller submodules:
-
OCP-T1/OCP-T2 registers
-
EMIFS registers
-
EMIFF registers
-
OCPI registers
Traffic Controller
OMAP3.2 Subsystem
91
Advertisement
Chapters
Table of Contents
