Texas Instruments OMAP5912 Reference Manual page 558

Ultralow-Power Device
Table 5. Clock Request to Clock Available Latencies
Latency Name
T1 4 x 32-kHz clock cycles + setup analog cell
T2 3 x 32-kHz clock cycles
T3 2 x 32-kHz clock cycles + setup analog cell
T4 1 x 32-kHz clock cycles
T5 1 x 32-kHz clock cycles + APLL lock time
T6 2 x 32-kHz cycles + setup analog cell + APLL lock time
T7 2 x 32-kHz clock cycles
T8 3 x 32-kHz clock cycles + setup analog cell
Table 6. Latencies for Each Peripheral Clock
Name Wake-Up Request
• PWRON_RESET
CK_REF
• MPU_RST
• RTC_ON_NOFF
• 32-kHz watchdog time-out
• Wake-up request
• UART2 requests system clock
• BCLKREQ
BCLK
• SOFT_REQ_REG[2]
• SDW_CLK_DIV_CTRL_SEL[1]
• MCLKREQ
MCLK
• SOFT_REQ_REG[6]
• COM_CLK_DIV_CTRL_SEL[1]
• CONF_MOD_COM_MCLK_12_48_SEL_R
40 Power Management
Description
Time to Get the Clock Active
Depending on Initial FSM State
Deep
Sleep
T1
System clock
T3
PLL clock
T6
System clock
T3
PLL clock
T6
Big Awake
Sleep
T2
T4 T5
T5 T5
T4 T4
T5 T5
SPRU753A