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DSP Memory Management Unit
Figure 17.
Translation for a Large Page Included in a Coarse Page
AP: Protection of the
B: Page Endianism
1 Big Endian
0 Little Endian
31
31
31
31
31
31
66
DSP Subsystem
Figure 17 and Figure 18 show how the physical address is built as a function
of the page sizes and hierarchy.
DSP virtual address
23
20 19
Table index
L2 table index
4
Translation table base
Translation base
25
Translation base
First level descriptor
Page table base address
Page table base address
Second level descriptor
Page base address
Physical address
Page base address
16
15
12
11
Page index
8
7 6
7 6
5
0
9
10
10
9
L2 table index
16
15
6
5
AP
16 15
Page index
0
15
0
2 1
0
Table
0
0
index
2 1
0
0
1
2 1
0
0
0
4
3
2
1
0
0 1
0
SPRU750A
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