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Table 77. DMA LCD Control Register (DMA_LCD_CTRL)
Bit
Name
15:9
RESERVED
8
LDP
7:6
LSP
SPRU755B
OMAP3_1_COMPATIBLE_DISABLE: Omap3.1 channel compatibility
-
control.
This bit is used to set DMA LCD channel programming model.
omap3_1_compatible_disable = 1: The LCD channel is in OMAP3.2 com-
patible mode.
omap3_1_compatible_disable = 0: The LCD channel is in OMAP3.1 com-
patible mode.
END_PROG: end of programming status bit
-
end_prog = 1: When LCD channel is in autoinitialization mode, it allows the
channel to reinitialize itself with a new channel context (the program regis-
ter set is copied to the active register set) after the current DMA channel
transfer has been finished. The end_prog bit automatically resets itself
when the new context has been loaded.
end_prog = 0: When LCD channel is in autoinitialization mode, and RE-
PEAT bit is 1, DMA continues LCD next transfer with the same channel
context. If REPEAT = 0, the channel does not reinitialize itself and does not
start a new transfer.
The end_prog bit is not considered if AUTO_INIT = 0.
SRC_AMODE_B1/SRC_AMODE_B2: Source addressing mode for
-
block1 or block2 transfer. This field is used to choose the addressing mode
on the source port of the channel.
src_amode_b1/b2 = 00: Reserved
src_amode_b1/b2 = 01: Post-incremented address
src_amode_b1/b2 = 10: Single index (element index)
src_amode_b1/b2 = 11: Double index (element and frame indexes)
There is no need for a dst_amode_b1/dst_amode_b2 because there is no
write address to a destination port in the LCD channel case.
Base Address = 0xFFFE E300, Offset Address = 0xC4
Function
Reserved.
LCD destination port (OMAP or external LCD
controller).
LCD source port. Memory source for the LCD
channel.
Direct Memory Access (DMA) Support
System DMA
R/W
Reset
R/W
ND
R/W
0
R/W
00
113
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