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5.14.2
BCLK and BCLKREQ
SPRU751A
J
Set ULPD COM_CLK_CTRL_DIV_SEL.COM_RATIO_SEL to the
desired ratio.
J
Set the COM_SYSCLK_PLLCLK_SEL bit to 0 in the ULPD
COM_CLK_CTRL_DIV_SEL register.
J
Set
the
COM_ULPD_PLL_CLK_REQ
COM_CLK_CTRL_DIV_SEL register.
Consequently, the 48MHz clock divided by the programmed ratio will be
available on MCLK. Use COM_ULPD_PLL_CLK_REQ to disable or re-enable
MCLK clock. Note that by setting COM_RATIO_SEL to 00000, 48MHz will be
available on MCLK.
The hardware request for BCLK, BCLKREQ (ball W15), is available in
multiplexing mode 0. It is active high. Using this request, the user can get the
system clock on BCLK (ball Y15).
To get the system clock on BCLK using a hardware request, the following
software procedure is used:
J
Set the COM_SYSCLK_PLLCLK_SEL bit to 1 in the ULPD
SDW_CLK_CTRL_DIV_SEL register.
J
Set
the
DIS_COM_MCLK_REQ
SOFT_DISABLE_REQ_REG register.
J
Set the SOFT_SDW_REQ bit to 0 in the ULPD SOFT_REQ_REG.
Consequently, setting BCLKREQ (W15) high puts the system clock on BCLK
(Y15). The software can mask out BCLKREQ, and deactivate BCLK by
changing SOFT_DIS_SDW_MCLK_REQ. When the system clock is output on
MCLK,
the
software
CLOCK_CTRL_REG.SDW_MCLK_INV to select the inactive level of BCLK.
A software request for BCLK is also available. Depending on the software
request used, BCLK can be:
J
48MHz coming from the ULPD APLL divided by a programmable ratio.
J
The system clock.
For the system clock on BCLK with a software request, the following software
procedure must be used:
J
Set the SDW_SYSCLK_PLLCLK_SEL bit to 1 in the ULPD
SDW_CLK_CTRL_DIV_SEL register.
J
Set
the
DIS_SDW_MCLK_REQ
SOFT_DISABLE_REQ_REG register.
OMAP5912 Clock Architecture
to
1
bit
to
0
can
also
use
bit
to
1
in
the
ULPD
in
the
ULPD
the
ULPD
in
the
ULPD
Clocks
57
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