Texas Instruments OMAP5912 Reference Manual page 117

Multimedia processor device overview and architecture

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Mode 5 Synchronous Burst 8x16-Bit Read Operation on Multiplexed

Address/Data 16-Bit Width Device (RDWST=2, FCLKDIV =0, ADVHOLD=0, OESETUP =

3, RDMODE=5). Data write-back on the bus after read completion.

FLASH.A(25:16)

FLASH.A.D(15:0)

FLASH.BE(1:0)

CS, ADV, and address are driven one REF_CLK cycle before the first

FLASH.CLK rising edge is provided externally. This ensures CS, ADV, and

address valid setup time to device clock rising edge to be met.

In case this one REF_CLK cycle advance is not enough to meet the setup

time requirement, the ADV pulse width can be extended by ADVHOLD.

The real access time start from CS & ADV & address setup time to device

clock rising edge valid.

Address hold time from ADV rising edge is guaranteed to be a minimum

of one REF_CLK (delay for direction to change from out to in).

FCLKDIV and OESETUP (REF_CLK) must be properly programmed to

prevent bus contention and to ensure that address hold time device

requirement is respected.

Delay time OEHOLD is disabled.

The ADV pulse width depends on ADVHOLD bit field of the Advanced CS

configuration register (see Table 28). ADV pulse width equals to:

(ADVHOLD + 1) REF_CLK + 1 TC_CK (M cycles in Figure 24)

OMAP3.2 Subsystem

Traffic Controller

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