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Figure 12.
Asynchronous 32-Bit Read Operation on a 16-Bit Multiplexed Address and
Data Memory. RDWST=2 FCLKDIV=0 OESETUP=2 OEHOLD = 0 ADVHOLD = 0
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A/D(15:0)/
FLASH.A(25:16)
FLASH.OE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY
44
OMAP3.2 Subsystem
N cycles
M cycles
Valid add1
OESETUP
-
The full-handshaking scheme is also valid in multiplexing mode. The
following diagram shows an asynchronous word16 read operation with a
16-bit multiplexed memory control by external ready pin.
Low
BTWST+1 TC cycles
Data valid
Valid add2
00
N cycles
Valid data2
SPRU749A
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