Texas Instruments OMAP5912 Reference Manual page 114

Traffic Controller
56 OMAP3.2 Subsystem
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In case this one REF_CLK cycle advance is not enough to meet the setup
time requirement, the ADV pulse width can be extended by ADVHOLD.
The real access time start from CS & ADV & address setup time to device
clock rising edge valid.
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The ADV pulse width depends on ADVHOLD bit field of the Advanced CS
configuration register (see Table 28). ADV pulse width equals:
J
(ADVHOLD + 1) REF_CLK + 1 TC_CK (M cycles in Figure 21)
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Modes 4−5 are by default in full-handshaking mode. FLASH.RDY is
monitored by the EMIFS to control read access time. FLASH.RDY must
be asserted synchronously to FLASH.CLK.
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The first access is completed when both internal RDWST wait state
expired and when FLASH.RDY is asserted by the external device.
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The internal initial wait state depends on RDWST bit field of the CS
configuration register. RWDST value must include the extra "non active"
output REF_CLK cycle used for CS & ADV & address setup time. Delay
equals:
J
(RDWST + 2) REF_CLK (N cycles in Figure 21)
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Read data are latched on each TC_CK rising edge corresponding to a
REF_CLK rising edge when FLASH.RDY has been sampled high on the
previous REF_CLK rising edge.
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The following in-burst access wait state only depends on the FLASH.RDY
state (RDWST expired).
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In mode 4, BAA control signal is asserted low on the first date sampling
REF_CLK rising edge and is maintained low during the full burst access.
BAA is kept high in mode 5 (no burst advance control is this mode).
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OE activation delay time from CS and address valid is programmable
through OESETUP bit field in the advanced CS configuration register.
Activation delay timing is equal to:
J
(OESETUP) REF_CLK
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Advanced time (OEHOLD) control is disabled (OEHOLD bit field doesn't
care).
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One TC_CK cycle after access completion (CS high) the data bus is driven
with the previous read value (see Figure 21for direction activation and
data copy timing).
SPRU749A