Texas Instruments OMAP5912 Reference Manual page 112

Multimedia processor device overview and architecture

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Traffic Controller

Asynchronous Page Mode 8x16-Bit Read With Page Crossing Operation on

16-Bit Width Device (RDWST=2, PGWST=0 FCLKDIV=1, RDMODE=1). Data write-back

on the bus after read completion.

FLASH.A(25:1)

FLASH.D(15:0)

FLASH.BE(1:0)

OMAP3.2 Subsystem

Delay equals to (PGWST + 1) REF_CLK (P cycles in Figure 19).

ADV (FLASH.ADV on ball L4) is kept low for the entire access.

Address drive time follows CS activation (no setup time guaranty).

Delay time (OESETUP) and advanced time (OEHOLD) are disabled

(OESETUP and OEHOLD bit fields don't care).

Address and data multiplexed scheme is not supported in mode 1−2−3.

Read data are latched on the TC_CK rising edge corresponding to the wait

state delay completion (initial and in page wait state).

One TC_CK cycle after access completion (CS high), the data bus is

driven with the previous read value (see Figure 19 for direction activation

and data copy timing).

In asynchronous mode, REF_CLK is not provided outside the EMIFS and

FLASH.CLK is kept low.

Page mode always follows the non-full-handshaking protocol and the

FLASH.RDY pin is never monitored whatever the full-handshaking bit field

value in the dynamic wait state register is.

Add1 Add2 Add3

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