Texas Instruments OMAP5912 Reference Manual page 118

Multimedia processor device overview and architecture

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Traffic Controller

Mode 5 Synchronous Burst 4x16-Bit Read Operation on Multiplexed

Address/Data 16-Bit Width Device (RDWST=4, FCLKDIV =0, ADVHOLD=1, OESETUP =

4, RDMODE=5). Data write-back on the bus after read completion.

FLASH.A/D(15:0)/

FLASH.A(25:16)

FLASH.BE(1:0)

OMAP3.2 Subsystem

Modes 4−5 are by default in full-handshaking mode. FLASH.RDY is

monitored by the EMIFS to control read access time. FLASH.RDY must

be asserted synchronously to REF_CLK.

The first access is completed when both internal RDWST wait state

expired and when ready pin is asserted by the external device.

The internal initial wait state depends on RDWST bit field of the CS

configuration register. RWDST value must include the extra nonactive

output REF_CLK cycle used for CS and ADV and address setup time.

Delay equals:

(RDWST + 2) REF_CLK (N cycles in Figure 24)

Read data is latched on each TC_CK rising edge corresponding to a

REF_CLK rising edge when FLASH.RDY has been sampled high on the

previous REF_CLK rising edge.

The following in-burst access wait state only depends on the FLASH.RDY

pin state (RDWST expired).

One TC_CK cycle after access completion (CS high), the data bus is

driven with the previous read value (see Figure 24 direction activation and

data copy timing).

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