Texas Instruments OMAP5912 Reference Manual page 111

Multimedia processor device overview and architecture

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Asynchronous Page Mode 4x16-Bit Read Operation on 16-Bit Width Device

(RDWST=2, PGWST=0 and FCLKDIV =1, RDMODE=2 ). Data write-back on the bus after

read completion.

FLASH.A(25:1)

FLASH.D(15:0)

FLASH.BE(1:0)

page length and word size (device width), the EMIFS can control device

page crossing during a burst request (4×word32) and inserts initial wait

state delay on purpose.

The delay between successive words in the page is controlled by the

PGWST bit field in the CS configuration register (in page wait state).

The REF_CLK is divided from TC_CK by a programmable value

contained in FCLKDIV bit field of the CS configuration register (Table 19).

The initial wait state depends on RDWST bit field of the CS configuration

(RDWST + 2) REF_CLK (N cycles in Figure 19)

The in page wait state depends on:

PGWST/WELEN[15:12] bit field if PGWSTEN=0 in CS configuration

PGWST[30:27] bit field if PGWSTEN=1 in CS configuration register

OMAP3.2 Subsystem

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