Figure 16.
Asynchronous 16-Bit Write Operation on a Multiplexed Address/16-Bit Data
Bus (WRWST = 1, WELEN = 3, FCLKDIV = 00 and ADVHOLD = 0)
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A/D(15:0)
FLASH.A(25:16)
FLASH.WE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY
SPRU749A
M
1 Flash clk
WA
N
Low
Write data
WA
Q
P cycles
Low
00
OMAP3.2 Subsystem
Traffic Controller
49