Texas Instruments OMAP5912 Reference Manual page 106

Traffic Controller
48 OMAP3.2 Subsystem
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The CS and address setup time from WE low is controlled by
programmable WRWST bit field of the CS configuration register (see
Table 19).
J
(WRWST + 1) REF_CLK (N cycles in Figure 15)
J
WRWST minimum pulse width is 1 REF_CLK.
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The ADV pulse width depends on ADVHOLD bit field of the advanced CS
configuration register (see Table 28). ADV pulse width equals:
J
(ADVHOLD + 1) REF_CLK (Mcycles in Figure 15)
J
ADV min pulse width is 1 REF_CLK.
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The WE pulse width depends on WELEN bit field of the CS configuration
register (see Table 19). WE pulse width equals to:
J
(WELEN + 1) REF_CLK (P cycles in Figure 15)
J
WE minimum pulse width is 1 REF_CLK.
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The CS and data hold time setup from WE high is fixed to one REF_CLK
(Q cycle in Figure 15).
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In asynchronous mode 0−1−2−3, REF_CLK is not provided outside the
EMIFS and FLASH.CLK is kept low. In synchronous mode 4−5 REF_CLK
is provided outside the EMIFS through FLASH.CLK. In synchronous
mode 7 REF_CLK is inverted and provided outside the EMIFS through the
FLASH.CLK (see mode 7).
SPRU749A