Texas Instruments OMAP5912 Reference Manual page 121

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Mode 4 Synchronous Burst 4x16-Bit Read Operation on 16-Bit Width Device

With Retiming on (RDWST=2, FCLKDIV =0, ADVHOLD=0, RDMODE=4). Data write-back

on the bus after read completion.

FLASH.A(25:1)

FLASH.D(15:0)

Retimed Flash

FLASH.BE(1:0)

The retiming mode is enabled through the RT bit field in the CS

configuration register. Retiming mode is only allowed in synchronous

modes 4−5−7 and has no effect on write accesses.

As in non-retimed mode, CS, ADV, Address, BE, OE, and BAA are driven

with respect to REF_CLK.

Modes 4 and 5 programming model and protocol behavior remain the

same as in non-retimed mode.

In retiming mode, the RDWST is still referenced to REF_CLK. The

retiming relaxed timing (extra delay for data valid) is included in the IC

timing parameters.

FLASH.RDY is also retimed with the Ret_REF_CLK. The retiming relaxed

timing (extra delay for ready valid) is included in the IC timing parameters.

Valid address

OMAP3.2 Subsystem

Traffic Controller

Î Î Î Î Î Î Î

Chapters

Table of Contents