Texas Instruments OMAP5912 Reference Manual page 104

Traffic Controller
Figure 14. Asynchronous 16-Bit Write Operation on a 16-Bit Width Device (WRWST=2,
WELEN=4 FCLKDIV=00 and ADVHOLD=1)
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A(25:1)
FLASH.D(15:0)
FLASH.WE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY
46 OMAP3.2 Subsystem
M
N
-
The REF_CLK is divided from TC_CK by a programmable value
contained in FCLKDIV bit field of the CS configuration register.
-
The CS and address setup time from WE low is controlled by
programmable WRWST bit field of the CS configuration register.
J
(WRWST + 1) REF_CLK (N cycles in Figure 14)
J
WRWST minimum pulse width is 1 REF_CLK.
-
The ADV pulse width depends on ADVHOLD bit field of the Advanced CS
configuration register (see Table 28). ADV pulse width equals:
J
(ADVHOLD + 1) REF_CLK (M cycles in Figure 14)
J
ADV minimum pulse width is 1 REF_CLK.
-
The WE pulse width depends on WELEN bit field of the CS configuration
register (see Table 19). WE pulse width equals:
J
(WELEN + 1) REF_CLK (P cycles in Figure 14)
J
WE minimum pulse width is 1 REF_CLK.
Low
Valid address
Write data
P cycles
Low
00
Q
SPRU749A