Table of Contents
Advertisement
Figure 11.
Asynchronous 16-Bit Read Operation With Multiplexed Address/Data Bus
Memory. RDWST=2 FCLKDIV=0 OESETUP=2 OEHOLD=0 ADVHOLD=0. Data write-back
on the bus after read completion.
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A/D(15:0)/
FLASH.A(25:16)
FLASH.OE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY
SPRU749A
M cycles
Valid address
OESETUP
-
Address drive time follows CS activation (no setup time guaranty).
Address setup time to ADV rising edge is controlled by ADVHOLD.
Address hold from ADV rising edge is guaranteed to be minimum one
REF_CLK (delay for direction to change from out to in). FCLKDIV and
OESETUP must be properly programmed to prevent bus contention and
to ensure that address hold time device requirement is respected.
-
During split read accesses and during burst read accesses, the CS signal
is deactivated for at least one TC_CK between two successive accesses.
CS pulse width high time can be extended by the BTWST field in the CS
configuration register (see also bus turn around and CS negation time
control).
J
CS pulse width high = (BTWST +1) TC_CK
Low
N cycles
Valid data (D0)
00
OMAP3.2 Subsystem
Traffic Controller
(D0)
43
Advertisement
Chapters
Table of Contents
