Serial Standby Control Register M (Sscm) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.14 Serial standby control register m (SSCm)

The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when
receiving CSI00 or UART0 serial data.
The SSCm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSCm register can be set with an 8-bit memory manipulation instruction with SSCmL.
Reset signal generation clears the SSCm register to 0000H.
Caution The maximum transfer rate in the SNOOZE mode is as follows.
 When using CSI00:
 When using UART0: 4800 bps only
Address: F0138H After reset: 0000H
Symbol 15 14
SSCm 0 0
SSECm
0
1
 The SSECm bit can be set to 1 or 0 only when both the SWCm and EOCmn bits are set to 1 during UART
reception in the SNOOZE mode. In other cases, clear the SSECm bit to 0.
 Setting SSECm, SWCm = 1, 0 is prohibited.
SWCm
0
1
 When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is
performed without operating the CPU (the SNOOZE mode).
 The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for
the CPU/peripheral hardware clock (f
 Even when using SNOOZE mode, be sure to set the SWCm bit to 0 in normal operation mode and change it to 1
just before shifting to STOP mode.
Also, be sure to change the SWCm bit to 0 after returning from STOP mode to normal operation mode.
Caution Setting SSECm, SWCm = 1, 0 is prohibited.
Figure 11-18. Interrupt in UART Reception Operation in SNOOZE Mode
EOCmn Bit
0
0
1
1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Up to 1 Mbps
Figure 11-17. Format of Serial Standby Control Register m (SSCm)
R/W
13 12 11 10
0 0 0 0
Selection of whether to enable or disable the generation of
communication error interrupts in the SNOOZE mode
Enable the generation of error interrupts (INTSRE0)
Disable the generation of error interrupts (INTSRE0)
Do not use the SNOOZE mode function.
Use the SNOOZE mode function.
CLK
SSECm Bit
0
1
0
1
9 8 7 6
0 0 0 0
Setting of the SNOOZE mode
). If any other clock is selected, specifying this mode is prohibited.
Reception Ended Successfully
INTSRx is generated.
INTSRx is generated.
INTSRx is generated.
INTSRx is generated.
CHAPTER 11 SERIAL ARRAY UNIT
5 4 3 2
0 0 0 0
Reception Ended in an Error
INTSRx is generated.
INTSRx is generated.
INTSRx is generated.
No interrupt is generated.
1 0
SS SWC
ECm m
332