Serial Mode Register Mn (Smrmn) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.3 Serial mode register mn (SMRmn)

The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock
(f ), specify whether the serial clock (f
MCK
and an interrupt source. This register is also used to invert the level of the receive data only in the UART mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0
bit can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Address: F0110H, F0111H (SMR00), F0112H, F0113H (SMR01)
Symbol 15 14
SMRmn CKS CCS
mn mn
CKS
mn
0 Operation clock CKm0 set by the SPSm register
1 Operation clock CKm1 set by the SPSm register
Operation clock (f
higher 7 bits of the SDRmn register, a transfer clock (f
CCS
mn
0 Divided operation clock f
1 Clock input f
Transfer clock f
error controller. When CCSmn = 0, the division ratio of operation clock (f
SDRmn register.
STS
mn
0 Only software trigger is valid (selected for CSI and UART transmission).
1 Valid edge of the R
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note The SMR01 register only.
Caution Be sure to clear bits 13 to 9, 7, and 4 to 2 (or bits 13 to 6, and 4 to 2 for the SMR00 register) to "0". Be
sure to set bit 5 to "1".
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00), q: UART number (q = 0)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
) may be input or not, set a start trigger, an operation mode (CSI or UART),
SCK
Figure 11-5. Format of Serial Mode Register mn (SMRmn) (1/2)
13 12 11 10
0 0 0 0
Selection of operation clock (f
) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
MCK
Selection of transfer clock (f
specified by the CKSmn bit
MCK
from the SCKp pin (slave transfer in CSI mode)
SCK
is used for the shift register, communication controller, output controller, interrupt controller, and
TCLK
Dq pin (selected for UART reception)
X
CHAPTER 11 SERIAL ARRAY UNIT
After reset: 0020H
9 8 7 6
0 STS 0 SIS
Note
mn mn0
Note
) of channel n
MCK
) is generated.
TCLK
) of channel n
TCLK
MCK
Selection of start trigger source
R/W
5 4 3 2
1 0 0 0
) is set by the higher 7 bits of the
1 0
MD MD
mn1 mn0
318