Mcasp Clocking; Mcasp Clocking Diagram; Emac Reference Clock Frequencies - Texas Instruments AM1802 Reference Manual

Peripheral Clocking
OSCIN PLL Multiplier
Frequency Register Setting Frequency
25 24
25 18
(1)
See Section 6.2 for explanation of POSTDIV divider modes.
(2)
Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7.

6.3.5 McASP Clocking

As shown in Figure
clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC
bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module.
The transmit and receive clocks are sourced internally or externally by configuring the McASP clock
control registers ACLKRCTL, AHCLKRCTL, ACLKXCTL, and AHCLKXCTL. If an external clock is driven
into a high-frequency master clock (AHCLKX or AHCLKR), the McASP module allows for a mixed clock
mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the
high-frequency master clock through a programmable divider.
When the internal clock source option is selected, the transmit and receive clocks are derived from the
PLL0_AUXCLK clock through programmable dividers.
PLL0_SYSCLK2
PLL1_SYSCLK2
68
Device Clocking
Table 6-7. EMAC Reference Clock Frequencies
Multiplier
600 MHz
450 MHz
6-6, the McASP peripheral requires multiple clock sources. Internally, the module
Figure 6-6. McASP Clocking Diagram
CFGCHIP3[ASYNC3_CLKSRC]
0
LPSC
1
PLL0_AUXCLK
Copyright © 2011, Texas Instruments Incorporated
POSTDIV
Post Divider Output
(1)
Mode Frequency
Div2 300 MHz
Div3 200 MHz
Div4 150 MHz
Div2 225 MHz
Div3 150 MHz
Div4 112.5 MHz
Module
Clock
TX/RX
Reference
Clock Clock
Generator
ACLKX
AHCLKX
ACLKR
AHCLKR
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PLLDIV7
Register
Setting PLL0_SYSCLK7
5 50 MHz
3 50 MHz
2 50 MHz
Not Applicable
2 50 MHz
Not Applicable
On Chip
McASP0
Frame Sync
Generator
AFSX AFSR
SPRUGX5A – May 2011
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(2)
(2)