Emac Reference Clock Frequencies - Texas Instruments AM1808 Technical Reference Manual

Peripheral Clocking
OSCIN PLL Multiplier
Frequency Register Setting
25 24
25 18
(1)
See Section 6.2 for explanation of POSTDIV divider modes.
(2)
Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7.
126
Device Clocking
Table 6-7. EMAC Reference Clock Frequencies
Multiplier Post Divider
(1)
Frequency Mode
600 MHz Div2
Div3
Div4
450 MHz Div2
Div3
Div4
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PLLDIV7
POSTDIV Output Register
Frequency Setting
300 MHz 5
200 MHz 3
150 MHz 2
225 MHz
150 MHz 2
112.5 MHz
SPRUH82C – April 2013 – Revised September 2016
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PLL0_SYSCLK7
50 MHz
50 MHz
50 MHz
(2)
Not Applicable
50 MHz
(2)
Not Applicable