Advertisement
www.ti.com
NOTE: The system clock version provided to the DPLL4 can be pre-divided by a factor of 6.5
before feeding the DPLL4. This is done in the PRM through a dedicated programmable
register. This divider is intended to be used in case a 13-MHz system clock is used so that
the DPLL4 can be locked at 864 MHz.
3.5.3.4.2.2 Peripheral Module Clocks
Table 3-34
lists the peripherals, DSS, and CAM functional clock frequency requirements. These
frequencies must be operational over the full VDD2 voltage range.
Module
MMC-SDIO[1,2,3]
McBSP[1, 5]
CAM
McSPI[1..4]
UART[1..4]
Display subsystem
SGX
I2C[1..3]
HDQ
GPTIMER1
GPTIMER[2..9]
GPTIMER[10, 11]
ICR
WDTIMER2
WDTIMER3
GPIO1
GPIO[2-6]
32-kHz sync timer
Bandgap/temp sensor
System control
3.5.3.5
External Clock Controls
Because the use of sys_32k and sys_altclk is described in
CM, these clock signals are not discussed here. This section discusses the remaining external clock
signals.
3.5.3.5.1 Clock Request (sys_clkreq) Control
The system clock request signal sys_clkreq is bidirectional.
In bypass mode in the system clock oscillator (see
device to request an external clock. In this case, the output buffer is driven as long as the system clock is
requested by the device; otherwise, it remains in high impedance. In this way, other external peripherals
can share the same clock request signal with the device.
If the PRM_POLCTRL[1] CLKREQ_POL bit = 1, the software must configure the SCM to select the
internal pulldown on the sys_clkreq pad, or an external pulldown is connected to the pad.
SWPU177N – December 2009 – Revised November 2010
Public Version
Table 3-34. Peripheral Module Functional Clock Frequencies
Functional Clock
CORE_48M_FCLK
DSS1_ALWON_FCLK
DSS2_ALWON_FCLK
CORE_96M_FCLK
CORE_12M_FCLK
GPTn_ALWON_FCLK
WKUP_32K_FCLK
PER_32K_ALWON_FCLK
WKUP_32K_FCLK
PER_32K_ALWON_FCLK
Copyright © 2009–2010, Texas Instruments Incorporated
96M_FCLK
96M_FCLK
CAM_MCLK
DSS_TV_FCLK
SGX_FCLK
GPT1_FCLK
GPTn_FCLK
32K_FCLK
32K_FCLK
CORE_L4_ICLK
Section
3.5.3.3.1, PRM, and
Section
3.5.3.5.2), it is an output signal driven by the
Power, Reset, and Clock Management
PRCM Functional Description
Frequency
96 MHz
96 MHz
Up to 216 MHz
48 MHz
Up to 173 MHz at nominal voltage
(OPP100), and up to 100 MHz at low
voltage (OPP50)
System clock
54 MHz
Up to 200 MHz
96 MHz
12 MHz
32-kHz (p) or system clock
32-kHz (p) or system clock
32-kHz or system clock
32 kHz
32 kHz
32 kHz
32 kHz
32 kHz (p)
32 kHz (p)
L4_ICLK
Section
3.5.3.3.2,
325
Advertisement
Chapters
