Operations; Status After Reset - Renesas M16C/64A Series User Manual

M16C/64A Group
6.4

Operations

6.4.1

Status after Reset

The status of SFRs after reset depends on the reset type. See the Reset Value column in 4. "Special
Function Registers (SFRs)". Table 6.7 lists Pin Status When RESET Pin Level is Low, Figure 6.2 shows
CPU Register Status after Reset, and Figure 6.3 shows Reset Sequence.
Pin Status When RESET Pin Level is Low
Table 6.7
Pin Name
Single-chip mode
(CNVSS = VSS)
P0 Input port
P1 Input port
P2, P3, P4_0
Input port
to P4_3
P4_4 Input port
P4_5 to P4_7 Input port
P5_0 Input port
P5_1 Input port
P5_2 Input port
P5_3 Input port
P5_4 Input port
P5_5 Input port
P5_6 Input port
P5_7 Input port
P6 to P10 Input port
Notes:
1. The pin status shown here is when the internal power supply voltage has stabilized after power-on.
The pin status is undefined until td(P-R) has elapsed after power-on.
2. Input a high-level signal.
3. Input a low-level signal.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Microprocessor mode (CNVSS = VCC1, P5_5 = high)
BYTE = VSS
Data input
Data input
Address output (undefined)
CS0 output
(high level is output)
Input port (pulled high)
WR output
(high level is output)
BHE output (undefined)
RD output
(high level is output)
BCLK output
HLDA output
(the output value depends on
the input to the HOLD pin)
HOLD input
(2)
ALE output
(low level is output)
RDY input
Input port
(1)
Status
BYTE = VCC1
Data input
Input port
Address output (undefined)
CS0 output
(high level is output)
Input port (pulled high)
WR output
(high level is output)
BHE output (undefined)
RD output
(high level is output)
BCLK output
HLDA output
(the output value depends on
the input to the HOLD pin)
HOLD input
(2)
ALE output
(low level is output)
RDY input
Input port
6. Resets
Boot mode
(CNVSS = VCC1,
P5_5 = low,
P5_0 = high)
Input port
Input port
Input port
Input port
Input port
CE input
(2)
Input port
Input port
Input port
Input port
EPM input
(3)
Input port
Input port
Input port
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