Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 498

Enhanced Local Bus Controller
• Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when OR
OR [TRLX] = 1.
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The timing diagram in
LCRR[CLKDIV] = 4 or 8. If LCRR[CLKDIV] = 2, LCSn asserts identically for OR
10.4.2.3.1 Programmable Wait State Configuration
The GPCM supports internal generation of transfer acknowledge. It allows between zero and 30 wait states
to be added to an access by programming OR
acknowledge is enabled if OR
before the wait state counter has expired (to allow for synchronization latency), the current memory cycle
is terminated by LGTA; otherwise it is terminated by the expiration of the wait state counter. Regardless
of the setting of OR [SETA], wait states prolong the assertion duration of both LOE and LWE
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manner. When TRLX = 1, the number of wait states inserted by the memory controller is doubled from
OR [SCY] cycles to 2×OR
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10.4.2.3.2 Chip-Select and Write Enable Negation Timing
Figure 10-32 shows a basic connection between the local bus and a static memory device. In this case,
LCSn is connected directly to CE of the memory device. The LWE[0:1] signals are connected to the
respective WE[1:0] signals on the memory device where each LWE[0:1] signal corresponds to a different
data byte.
LCLK
LAD
LALE
A
TA
LCS n
LWE n
LOE
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 4, 8)
As Figure 10-36 shows, the timing for LCSn is the same as for the latched address. The strobes for the
transaction are supplied by LOE or LWE
case shown in the figure). OR
strobe negation in write cycles. When this attribute is asserted, the strobe is negated one quarter of a clock
before the normal case provided that LCRR[CLDIV] = 4 or 8. For example, when ACS = 00 and
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-50
Figure 10-33 shows two chip-select assertion timings for the case
[SETA] = 0. If LGTA is asserted externally two bus clock cycles or more
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[SCY] cycles, allowing a maximum of 30 wait states.
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Address
Figure 10-36. GPCM Basic Write Timing
, depending on the transaction direction—read or write (write
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[CSNT], along with ORn[TRLX], control the timing for the appropriate
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[SCY] and OR [TRLX]. Internal generation of transfer
n n
Write Data
Latched Address
SCY = 1
[XACS] = 1 and
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[ACS] = 10 or 11.
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CSNT = 1
Freescale Semiconductor
in the same
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