Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 220

System Configuration
5.2.4.7 DDR Local Access Window n Base Address Registers
(DDRLAWBAR0–DDRLAWBAR1)
The DDR local access window n base address registers (DDRLAWBAR0–DDRLAWBAR1) are shown
in Figure 5-8.
Offset 0xA0
0xA8
0
R
W
Reset
1
The reset value of DDRLAWBAR0[BASE_ADDR] depends on the reset configuration word high values. See
"DDRLAWBAR0[BASE_ADDR] Reset Value ,"
Figure 5-8. DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1)
Table 5-15 defines the bit fields of DDRLAWBAR0
'
Bits Name
0–19 BASE_ADDR
20–31 —
5.2.4.7.1 DDRLAWBAR0[BASE_ADDR] Reset Value
The core may use a DDR SDRAM device to fetch its boot vector. For this purpose, the
DDRLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration
word high BMS field.
Table 5-16 defines the reset value DDRLAWBAR0.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-12
BASE_ADDR
for a detailed description
Table 5-15. DDRLAWBAR0–DDRLAWBAR1 Bit Settings
Identifies the 20 most-significant address bits of the base of local access window n . The specified
base address should be aligned to the window size, as defined by DDRLAWAR n [SIZE].
Reserved. Write has no effect, read returns 0.
Table 5-16. DDRLAWBAR0[BASE_ADDR] Reset Value
RCWHR[BMS]
0
1
19 20
1
All zeros
DDRLAWBAR1.
–
Description
DDRLAWBAR0[BASE_ADDR]
Reset Value
0x00000
0xFF800
Access: Read/Write
31
—
Section 5.2.4.7.1,
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