Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 366

Integrated Programmable Interrupt Controller (IPIC)
Bits Name
0 — Write ignored, read = 0
1–7 HPI Highest priority interrupt. Specifies the 7-bit unique interrupt number/vector (see
interrupt controller interrupt source that is advanced to the highest priority in the IPIC priority table (see
Table 8-31). HPI can be modified dynamically.
8 — Write ignored, read = 0
9 MPSB Mixed interrupts priority scheme for group B. Selects the relative MIXB priority scheme. It cannot be changed
dynamically.
0 Grouped. The MIXBs are grouped by priority at the top of the table.
1 Spread. The MIXBs are spread by priority in the table.
10 MPSA Mixed interrupts priority scheme for group A. Selects the relative MIXA priority scheme. It cannot be changed
dynamically.
0 Grouped. The MIXAs are grouped by priority at the top of the table.
1 Spread. The MIXAs are spread by priority in the table.
11 — Write ignored, read = 0
12 IPSD Internal interrupts priority scheme for group D. Selects the relative SYSD priority scheme. It cannot be changed
dynamically.
0 Grouped. The SYSDs are grouped by priority at the top of the table.
1 Spread. The SYSDs are spread by priority in the table.
13 IPSC Internal interrupts priority scheme for group C. Selects the relative SYSC priority scheme. It cannot be changed
dynamically.
0 Grouped. The SYSCs are grouped by priority at the top of the table.
1 Spread. The SYSCs are spread by priority in the table.
14 IPSB Internal interrupts priority scheme for group B. Selects the relative SYSB priority scheme. It cannot be changed
dynamically.
0 Grouped. The SYSBs are grouped by priority at the top of the table.
1 Spread. The SYSBs are spread by priority in the table.
15 IPSA Internal interrupts priority scheme for group A. Selects the relative SYSA priority scheme. It cannot be changed
dynamically.
0 Grouped. The SYSAs are grouped by priority at the top of the table.
1 Spread. The SYSAs are spread by priority in the table.
16–21 — Write ignored, read = 0
HPIT HPI priority position IPIC output interrupt type. Defines which type of IPIC output interrupt signal ( int , cint , or
22–23
smi ) asserts its request to the core in the HPI priority position. These bits cannot be changed dynamically. (If
software really wants to change it, it has to make sure the corresponding interrupt source is masked or it won't
happen during the change).
The definition of HPIT is as follows:
00 int request is asserted to the core for HPI.
01 smi request is asserted to the core for HPI.
10 cint request is asserted to the core for HPI.
11 Reserved.
24–31 — Write ignored, read = 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
8-8
Table 8-4. SICFR Field Descriptions
Description
Table 8-6) of the single
Freescale Semiconductor