Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 950

Universal Serial Bus Interface
Table 16-18. ENDPOINTLISTADDR Register Field Descriptions
Bits Name
31–11 EPBASE Endpoint list address. Address of the top of the endpoint list.
10–0 — Reserved, should be cleared.
16.3.2.10 Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on the initiator (master) interface.
Offset 0x2_3160
31
R
W
Reset 0 0 0 0 0
Bits Name
31–16 — Reserved, should be cleared.
15–8 TXPBURST Programable TX burst length. This register represents the maximum length of a burst in 32-bit words
while moving data from system memory to the USB bus. Must not be set to greater that 16.
7–0 RXPBURST Programable RX burst length. This register represents the maximum length of a burst in 32-bit words
while moving data from the USB bus to system memory. Must not be set to greater than 16.
16.3.2.11 Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on device DMA transfers. It is only used in host mode.
The fields in this register control performance tuning associated with how the USB DR module posts data
to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance
include the how much data to post into the FIFO and an estimate for how long that operation should take
in the target system.
Definitions:
T = Standard packet overhead
0
T = Time to send data payload
1
T = Total Packet Flight Time (send-only) packet (T
s
T = Time to fetch packet into TX FIFO up to specified level.
ff
T = Total Packet Time (fetch and send) packet (T
p
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-22
—
0 0 0 0 0 0 0 0
Figure 16-16. Master Interface Data Burst Size (BURSTSIZE)
Table 16-19. BURSTSIZE Register Field Descriptions
Description
16 15
TXPBURST
0 0 0 0 0 0 1 0
Description
= T + T )
s 0 1
= T + T )
p ff s
Access: Read/Write
8 7
RXPBURST
0 0 0 0 0 0 1 0
Freescale Semiconductor
0
0 0 0