Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 253

Table 5-47 describes of the external PIT signal.
Signal I/O
PIT_CLK I This signal is used as the timebase for the periodic interval timer module.
Meaning
Timing
5.6.5 PIT Memory Map/Register Definition
The PIT programmable register map occupies 32 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All PIT registers are 32 bits wide and reside on 32-bit address boundaries and should only be accessed as
32-bit quantities.
All addresses used in this chapter are offsets from PIT base, as defined in
Table 5-48 shows the PIT memory map.
Offset
0x00 Periodic interval timer control register (PTCNR)
0x04 Periodic interval timer load register (PTLDR)
0x08 Periodic interval timer prescale register (PTPSR)
0x0C Periodic interval timer counter register (PTCTR)
0x10 Periodic interval timer event register (PTEVR)
0x14–0x1F Reserved
5.6.5.1 Periodic Interval Timer Control Register (PTCNR)
The periodic interval timer control register (PTCNR), shown in
PIT functions. The register can be read at any time.
Offset 0x00
0
R
W
Reset
Figure 5-33. Periodic Interval Timer Control Register (PTCNR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 5-47. PIT External Signal—Detailed Signal Descriptions
State
Table 5-48. PIT Register Address Map
Register
—
Description
—
—
Chapter 2, "Memory Map."
Access
R/W
R/W
R/W
R
w1c
—
Figure 5-33, is used to enable the different
23
All zeros
System Configuration
Section/
Reset Value
Page
0x0000_0000 5.6.5.1/5-45
0x0000_0000 5.6.5.2/5-46
0x0000_0000 5.6.5.3/5-47
0x0000_0000 5.6.5.4/5-47
0x0000_0000 5.6.5.5/5-47
—
Access: Read/Write
24 25 26
CLEN CLIN —
30 31
PIM
5-45