Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 332

e300 Processor Core Overview
• Section 7.3.6, "Instruction Timing,"
provided by the superscalar, parallel execution supported by the PowerPC architecture and the
e300 core.
• Section 7.1.6, "Bus Interface Unit (BIU),"
The e300 core is a high-performance, superscalar processor core. The PowerPC architecture allows
optimizing compilers to schedule instructions to maximize performance through efficient use of the
PowerPC instruction set and register model. The multiple, independent execution units allow compilers to
optimize instruction throughput. Compilers that take advantage of the flexibility of the PowerPC
architecture can additionally optimize system performance.
The following sections summarize the features of the core, including both those that are defined by the
architecture and those that are unique to the various core implementations.
Specific features of the core are listed in
7.3.1 Register Model
The PowerPC architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are provided as immediate values
embedded in the instruction opcode. The three-register instruction format allows specification of a target
register distinct from the two-source operands. Load and store instructions transfer data between registers
and memory.
The e300 core has two levels of privilege: supervisor mode of operation (typically used by the operating
system) and user mode of operation (used by the application software). The programming models
incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers.
Each core also has its own unique set of hardware implementation (HID) registers.
Having access to privileged instructions, registers, and other resources allows the operating system to
control the application environment (providing virtual memory and protecting operating system and
critical machine resources). Instructions that control the state of the e300 core, the address translation
mechanism, and supervisor registers can be executed only when the core is operating in supervisor mode.
Figure 7-2 shows all the core registers available at the user and supervisor level. The numbers to the right
of the SPRs indicate the number that is used in the syntax of the instruction operands for the move to/from
SPR instructions.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
7-14
provides a general description of the instruction timing
describes the signals implemented on the core.
Section 7.1.1, "Features."
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