Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 383

8.5.16 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)
Each implemented bit SIFCR_H and SIFCR_L, shown in
internal interrupt source. When a bit is set, the interrupt controller generates the corresponding interrupt
(sets the corresponding SIPNR bit).The SIFCR can be read by the user at any time.
Offset 0x50
0
R
W
Reset
Figure 8-19. System Internal Interrupt Force Register (SIFCR_H)
Table 8-25 defines the bit fields of SIFCR_H.
Bits Name
INT n Each implemented bit, listed in
0–31
interrupt by setting the corresponding SIFCR x bit. SIFCR n bit positions are not changed according to their
relative priority.
Writes to unimplemented (reserved) bits are ignored; read = 0
SIFCR_L is shown in
Offset 0x54
0
R
W
Reset
Figure 8-20. System Internal Interrupt Force Register (SIFCR_L)
Table 8-26 defines the bit fields of SIFCR_L.
Bits Name
0–31 INT n Each implemented bit, listed in
interrupt by setting the corresponding SIFCR x bit. SIFCR x bit positions are not changed according to their
relative priority.
Writes to unimplemented (reserved) bits are ignored; read = 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
n (Implemented bits are listed in
INT
Table 8-25. SIFCR_H Field Descriptions
Table
Figure 8-20.
INT n (Implemented bits are listed in
Table 8-26. SIFCR_L Field Descriptions
Table
Integrated Programmable Interrupt Controller (IPIC)
Figure 8-19
Table
All zeros
Description
8-7, corresponds to an internal interrupt source. The user forces an
Table
All zeros
Description
8-9, corresponds to an internal interrupt source. The user forces an
and Figure 8-20, corresponds to an
Access: Read/write
8-7.)
Access: Read/write
8-9).
31
31
8-25