Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 772

Enhanced Three-Speed Ethernet Controllers
Bits Name
29 EN5 Receive queue 5 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
30 EN6 Receive queue 6 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
31 EN7 Receive queue 7 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
15.5.3.3.5 Receive Bit Field Extract Control Register (RBIFX)
The RBIFX register provides a set of four 6-bit offsets for locating up to four octets in a received frame
and passing them to the receive queue filer as the user-defined ARB property. Through RBIFX a custom
ARB filer property can be constructed from arbitrary bytes, which allows frame filing on the basis of
bitfields not ordinarily provided to the filer, such as bits from the Ethernet preamble or TCP flags. The
value of property ARB is the concatenation of {B0, B1, B2, B3} to 32-bits, where B0–B3 are the bytes as
defined by RBIFX.
Figure 15-26 describes the definition for the RBIFX register.
Offset eTSEC1:0x2_4330; eTSEC2:0x2_5330
0 1 2
R
B0CTL B0OFFSET
W
Reset
Table 15-31 describes the RBIFX register.
\
Bits Name
0–1 B0CTL Location of byte 0 of property ARB.
00 Byte 0 is not extracted, and appears as zero in property ARB.
01 Byte 0 is located in the received frame at offset (B0OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
2–7 B0OFFSET Offset relative to the header defined by B0CTL that locates byte 0 of property ARB. An effective offset
of zero points to the first byte of the specified header.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-54
Table 15-30. RQUEUE Field Descriptions (continued)
7 8 9 10
B1CTL B1OFFSET
Figure 15-26. RBIFX Register Definition
Table 15-31. RBIFX Field Descriptions
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B0OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
Description
15 16 17 18
B2CTL B2OFFSET
All zeros
Description
Access: Read/Write
23 24 25 26
B3CTL B3OFFSET
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