Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 110

Memory Map
Offset
0x00118 System I/O configuration register high (SICRH)
0x0011C– Reserved
0x00124
0x00128 DDR control driver register (DDRCDR)
0x0012C DDR debug status register (DDRDSR)
0x00130– Reserved
0x0014C
0x00150– Reserved
0x001FC
0x0–0x3 Reserved
0x4 System watchdog control register (SWCRR)
0x8 System watchdog count register (SWCNR)
0xC–0xD Reserved
0xE System watchdog service register (SWSRR)
0x00 Real time counter control register (RTCNR)
0x04 Real time counter load register (RTLDR)
0x08 Real time counter prescale register (RTPSR)
0x0C Real time counter register (RTCTR)
0x10 Real time counter event register (RTEVR)
0x14 Real time counter alarm register (RTALR)
0x18–0x1F Reserved
0x00 Periodic interval timer control register (PTCNR)
0x04 Periodic interval timer load register (PTLDR)
0x08 Periodic interval timer prescale register (PTPSR)
0x0C Periodic interval timer counter register (PTCTR)
0x10 Periodic interval timer event register (PTEVR)
0x14–0x1F Reserved
0x00 Timer 1 and 2 global timers configuration register
(GTCFR1)
0x01–0x03 Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-6
Table 2-2. Memory Map (continued)
Register
Watchdog Timer (WDT) Registers
Real Time Clock Module Registers (RTC)
Periodic Interval Timer (PIT) Registers
Global Timers Module 1
Access Reset
R/W
0x0000_0000
— —
R/W 0x0004_0000
R 0x3300_0000
— —
— —
— —
R/W 0xFFFF_0003
or
9
0xFFFF_0007
R 0x0000_FFFF
— —
R/W 0x0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
w1c 0x0000_0000
R/W 0xFFFF_FFFF
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
w1c 0x0000_0000
— —
R/W 0x00
— —
Freescale Semiconductor
Section/Page
5.3.2.6/5-23
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5.3.2.8/5-27
5.3.2.9/5-29
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5.4.4.1/5-31
5.4.4.2/5-32
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5.4.4.3/5-33
5.5.5.1/5-38
5.5.5.2/5-39
5.5.5.3/5-40
5.5.5.4/5-40
5.5.5.5/5-41
5.5.5.6/5-41
5.6.5.1/5-45
5.6.5.2/5-46
5.6.5.3/5-47
5.6.5.4/5-47
5.6.5.5/5-47
5.7.5.1/5-55
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