Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 942

Universal Serial Bus Interface
Table 16-10. USBCMD Register Field Descriptions (continued)
Bits Name
1 RST Controller reset. Software uses this bit to reset the controller. This bit is cleared by the controller when the
reset process is complete. Software cannot terminate the reset process early by writing a zero to this
register.
Host mode:
• When software sets this bit, the host controller resets its internal pipelines, timers, counters, state
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software should not set this bit when
USBSTS[HCH] is a zero. Attempting to reset an actively running host controller will result in undefined
behavior.
Device mode:
• When software sets this bit, the USB DR controller resets its internal pipelines, timers, counters, state
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. Writing a one to this bit in device mode is not recommended.
0 RS Run/Stop.
Host mode:
• When this bit is set, the controller proceeds with the execution of the schedule. The controller continues
execution as long as this bit is set. When this bit is set to 0, the host controller completes the current
transaction on the USB and then halts. The USBSTS[HCH] bit indicates when the USB DR controller has
finished the transaction and has entered the stopped state. Software should not write a one to this field
unless the controller is in the halted state (that is, USBSTS[HCH] is a one).
Device mode:
• Setting this bit will cause the USB DR controller to enable a pull-up on D+ and initiate an attach event.
This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent an attach event before the
controller has been properly initialized. Clearing this bit will cause a detach event.
0 Stop
1 Run
16.3.2.2 USB Status Register (USBSTS)
This register indicates various states of the USB DR module and any pending interrupts. This register does
not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register
by writing a 1 to them (indicated by a w1c in the bit's W cell in
Offset 0x2_3144
31
R
W
Reset
15 14 13
R AS PS RCL
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-14
12 11 10 9
HCH ULPII
— —
Figure 16-9. USB Status Register (USBSTS)
Description
Figure 16-9).
—
All zeros
8 7 6 5
SLI SRI URI AAI
w1c w1c w1c w1c
All zeros
Access: Mixed
4 3 2 1
SEI FRI PCI UEI
w1c w1c w1c w1c
Freescale Semiconductor
16
0
UI
w1c