Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 340

e300 Processor Core Overview
Bits Name
17 DCE Data cache enable
0 The data cache is neither accessed nor updated. All pages are accessed as if they were marked
1 The data cache is enabled
18 ILOCK Instruction cache lock
0 Normal operation
1 The entire instruction cache is locked (that is, all eight ways of the cache are locked). A locked cache
To prevent locking during a cache access, an isync instruction must precede the setting of ILOCK.
19 DLOCK Data cache lock
0 Normal operation
1 The entire data cache is locked (that is, all eight ways of the cache are locked). A locked cache
To prevent locking during a cache access, a sync instruction must precede the setting of DLOCK.
20 ICFI Instruction cache Flash invalidate
0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation begins
1 An invalidate operation is issued that marks the state of each instruction cache block as invalid.
For the e300 core, the proper use of the ICFI and DCFI bits is to set and clear them with two consecutive
mtspr operations.
21 DCFI Data cache Flash invalidate
0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins (usually
1 An invalidate operation is issued that marks the state of each data cache block as invalid without
For the e300 core, the proper use of the ICFI and DCFI bits is to set and clear them with two consecutive
mtspr operations.
22–23 — Reserved, should be cleared.
24 IFEM Enable M bit on bus for instruction fetches
0 M bit not reflected on bus for instruction fetches. Instruction fetches are treated as nonglobal on the
1 Instruction fetches reflect the M bit from the WIM settings
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Table 7-2. e300 HID0 Bit Descriptions (continued)
cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache operations)
are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored and all data
read and write accesses are propagated to the CSB as single-beat transactions. For those
transactions, however, ci reflects the state of the I bit in the MMU for that page regardless of cache
disabled status. DCE is zero at power-up.
supplies data normally on a hit, but the access is treated as a cache-inhibited transaction on a miss.
On a miss, the transaction to the bus is single-beat; however, ci still reflects the state of the I bit in the
MMU for that page independent of cache locked or disabled status.
supplies data normally on a hit, but is treated as a cache-inhibited transaction on a miss. On a miss,
the transaction to the bus is single-beat; however, ci still reflects the state of the I bit in the MMU for
that page independent of cache locked or disabled status. A snoop hit to a locked L1 data cache
performs as if the cache were not locked. A cache block invalidated by a snoop remains invalid until
the cache is unlocked.
(usually the next cycle after the write operation to the register). The instruction cache must be
enabled for the invalidation to occur.
Cache access is blocked during this time. Setting ICFI clears all the valid bits of the blocks and the
PLRU bits to point to way L0 of each set.
the next cycle after the write operation to the register). The data cache must be enabled for the
invalidation to occur.
writing back modified cache blocks to memory. Cache access is blocked during this time. Bus
accesses to the cache are signaled as a miss during invalidate-all operations. Setting DCFI clears all
the valid bits of the blocks and the PLRU bits to point to way L0 of each set.
bus.
Function
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