Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 982

Universal Serial Bus Interface
Table 16-47. Endpoint and Transaction Translator Characteristics
Bits Name
31 I/O
30–24 Port Number
23 —
22–16 Hub Address
15–12 —
11–8 EndPt
7 —
6–0 Device Address Selects the specific device serving as the data source or sink.
Bits Name
31–16 —
15–8 µFrame C-mask Split completion mask. This field (along with the Active and SplitX- state fields in the status byte) is
7–0 µFrame S-mask Split start mask. This field (along with the Active and SplitX-state fields in the Status byte) is used
16.5.4.3 siTD Transfer State
DWords 3–6 manage the state of the transfer.
Bits Name
31 ioc Interrupt on complete
0 Do not interrupt when transaction is complete.
1 Do interrupt when transaction is complete. When the host controller determines that the split
30 P Page select. Indicates which data page pointer should be concatenated with the CurrentOffset field
to construct a data buffer pointer
0 Selects Page 0 pointer
1 Selects Page 1 pointer
The host controller is not required to write this field back when the siTD is retired (Active bit
transitioned from a one to a zero).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Direction (I/O). This field encodes whether the full-speed transaction should be an IN or OUT.
0 OUT
1 IN
This field is the port number of the recipient transaction translator.
Reserved, should be cleared. Bit reserved and should be cleared.
This field holds the device address of the companion controllers' hub.
Reserved, should be cleared. Field reserved and should be cleared.
Endpoint Number. Selects the particular endpoint number on the device serving as the data source
or sink.
Reserved, should be cleared. Bit is reserved for future use. It should be cleared.
Table 16-48. Micro-Frame Schedule Control
Reserved, should be cleared. This field reserved for future use. It should be cleared.
used to determine during which micro-frames the host controller should execute complete-split
transactions. When the criteria for using this field is met, an all-zeros value has undefined behavior.
The host controller uses the value of the three low-order bits of the FRINDEX register to index into
this bit field. If the FRINDEX register value indexes to a position where the µFrame C-Mask field is
a one, this siTD is a candidate for transaction execution. There may be more than one bit in this
mask set.
to determine during which micro-frames the host controller should execute start-split transactions.
The host controller uses the value of the three low-order bits of the FRINDEX register to index into
this bit field. If the FRINDEX register value indexes to a position where the µFrame S-mask field is
a one, then this siTD is a candidate for transaction execution. An all zeros value in this field, in
combination with existing periodic frame list has undefined results.
Table 16-49. siTD Transfer Status and Control
transaction has completed it will assert a hardware interrupt at the next interrupt threshold.
Description
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