Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 181

Table 4-11 defines the reset configuration word high bit fields.
Bits Name
0 PCIHOST PCI host mode.
See
1 — Reserved, should be cleared.
2 PCIARB PCI internal arbiter mode. Enables the on-chip PCI arbiter.
0 On-chip PCI arbiter is disabled. External arbitration is required.
1 On-chip PCI arbiter is enabled.
The value of PCIARB also defines the function of the PCI arbitration signals that are multiplexed with
CompactPCI signals, as follows:
3 — Reserved, should be cleared.
4 COREDIS Core disable mode. Specifies the e300 core mode out of reset. If COREDIS is set, the core cannot fetch
boot code until it is configured by an external master. The external master frees the core to boot by
clearing the COREDIS bit in the arbiter configuration register as described in
Configuration Register (ACR)."
This bit must be set when the boot sequencer is enabled to initiate the device (BOOTSEQ is not 0b00).
Otherwise, unpredictable behavior occurs.
0 The core can boot without waiting for configuration by an external master.
1 Core boot holdoff mode. The core is prevented from booting until it is configured by an external
5 BMS Boot memory space.
See
6–7 BOOTSEQ Boot sequencer configuration.
See
8 SWEN Software watchdog enable. Selects whether the software watchdog is enabled to start counting down
immediately when coming out of reset. The user can override this value by writing to the system
watchdog control register (SWCRR[SWEN]) during system initialization.
0 Disabled
1 Enabled
9–11 ROMLOC Boot ROM interface location.
This bit combined with bit RLEXT determines where the device boots from. See
ROM Location,"
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 4-11. Reset Configuration Word High Bit Settings
Section 4.3.2.2.1, "PCI Host/Agent
master.
Section 4.3.2.2.2, "Boot Memory Space
Section 4.3.2.2.3, "Boot Sequencer
for more information.
Description
Configuration," for more information.
Pin Function When Pin Function When
PCIARB = 0 PCIARB = 1
CPCI_HS_ES PCI_REQ[1]
CPCI_HS_LED PCI_GNT[1]
CPCI_HS_ENUM PCI_GNT[2]
(BMS)," for more information.
Configuration," for more information.
Reset, Clocking, and Initialization
Section 6.2.1, "Arbiter
Section 4.3.2.2.4, "Boot
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