Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 933

Signal
USBDR_STP
USBDR_PWRFAULT
USBDR_PCTL0
USBDR_PCTL1
USBDR_TXRXD[7:0]
16.2.3 PHY Clocks
The USBDR_CLK input provides the clocking signal for the ULPI PHY interface. The clock is 60 MHz.
Detailed clock specifications are given in the appropriate hardware specifications document.
16.3 Memory Map/Register Definitions
This section provides the memory map and detailed descriptions of all USB interface registers. The
memory map of the USB interface is shown in
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-2. ULPI Signal Descriptions (continued)
I/O
O Stop. USBDR_STP indicates the end of a transfer on the bus.
State Asserted—USB asserts this signal for 1 clock cycle to stop the data stream
Meaning currently on the bus. If USB port is sending data to the PHY, USBDR_STP
indicates the last byte of data was previously on the bus. If the PHY is
sending data to USB port, USBDR_STP forces the PHY to end its transfer,
negate USBDR_DIR and relinquish control of the data bus to the USB port.
Negated—Indicates normal operation.
Timing Synchronous to PHY_CLK.
I Power fault. USBDR_PWRFAULT indicates whether a power fault occurred on the USB port
Vbus.
State Asserted—Indicates that a Vbus fault occurred. Applications that support power
Meaning switching must shut down Vbus power.
Negated—Indicates normal operation.
Timing Synchronous to PHY_CLK.
O Port control 0. USBDR_PCTL0 controls the port status indicator LED 0 when in host mode.
State Asserted—LED on.
Meaning Negated—LED off.
Timing Synchronous to PHY_CLK.
O Port control 1. USBDR_PCTL1 controls the port status indicator LED 1 when in host mode.
State Asserted—LED on.
Meaning Negated—LED off.
Timing Synchronous to PHY_CLK.
I/O Data bit n . USBDR_TXRXD n is bit n of the 8-bit (USBDR_TXRXD7–USBDR_TXRXD0),
uni-directional data bus used to carry USB, register, and interrupt data between the PHY and
the USB controller.
Asserted—Data bit n is 1.
State
Meaning Negated—Data bit n is 0.
Timing Synchronous to PHY_CLK.
Description
Table 16-3.
Universal Serial Bus Interface
16-5