Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 453

Alternate
Name
Function(s)
LGPL3/ LGPL3
LFWP
LFWP
LGTA/ LGTA
LFRB/
LFRB
LGPL4/
LUPWAIT
LGPL4
LUPWAIT
LGPL5 —
LBCTL —
LA[0:25] —
LAD[0:15] —
LCLK[0:1] —
LDVAL —
LSRCID[0:4] —
Table 10-2 shows the detailed external signal descriptions for the eLBC.
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions
Signal I/O
LALE O External address latch enable. The local bus memory controller provides control for an external address
latch, which allows address and data to be multiplexed on the device pins.
State
Meaning
LCS[0:3] O Chip selects. Four chip selects are provided that are mutually exclusive.
State
Meaning
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 10-1. Signal Properties—Summary (continued)
Mode
UPM General purpose line 3
FCM Flash write protect
GPCM Transaction termination
FCM Flash ready/busy, open-drain shared pin
UPM General purpose line 4
UPM External device wait
UPM General purpose line 5
— Data buffer control
— Non-multiplexed address bus
— Multiplexed address/data bus
— Local bus clocks
eLBC debug Local bus data valid
eLBC debug Local bus source ID
Asserted/Negated—LALE is asserted with the address at the beginning of each memory
controller transaction. The number of cycles for which it is asserted is governed by the
ORn[EAD] and LCRR[EADC] fields. Note that no other control signals are asserted
during the assertion of LALE.
Asserted/Negated—Used to enable specific memory devices or peripherals connected to the
eLBC. LCS[0:3] are provided on a per-bank basis with LCS0 corresponding to the chip
select for memory bank 0, which has the memory type and attributes defined by BR0 and
OR0.
Descriptions
Description
Enhanced Local Bus Controller
No. of Reset State
I/O
Signals (Outputs)
1 O Reset_cfg
1
1 I High-Z
1 I
1 O
1 I
1 O Reset_cfg
1 O
26 O
16 I/O
2 O Driven
1 O
5 O
10-5