Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 503

LCLK
LAD
Rd. Address
LALE
A
TA
LCS n
LCSy
LBCTL
LOE
(TRLX = 0, EHTR = 1, One-Cycle Extended Hold Time on Reads)
10.4.2.4 External Access Termination (LGTA)
External access termination is supported by the GPCM using the asynchronous LGTA input signal, which
is synchronized and sampled internally by the local bus. If, during assertion of LCSn, the sampled LGTA
signal is asserted, it is converted to an internal generation of transfer acknowledge, which terminates the
current GPCM access (regardless of the setting of OR
bus cycle to be effective. Note that because LGTA is synchronized, bus termination occurs two cycles after
LGTA assertion, so in case of read cycle, the device still must drive data as long as LOE is asserted.
The user selects whether transfer acknowledge is generated internally or externally (LGTA) by
programming OR [SETA]. Asserting LGTA always terminates an access, even if OR
n
transfer acknowledge generation), but it is the only means by which an access can be terminated if
OR [SETA] = 1. The timing of LGTA is illustrated by the example in
n
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Read Data
Extended hold
Latched Read Address
Figure 10-42. GPCM Read Followed by Write
Wr. Address
Bus turnaround
[SETA]). LGTA should be asserted for at least one
n
Figure
Enhanced Local Bus Controller
Wr. Data
Wr. Address
[SETA] = 0 (internal
n
10-43.
10-55