Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 271

event, corresponding GTEVRn[REF] or GTEVRn[CAP] is set and a maskable interrupt request is issued
to the interrupt controller.
• Normal gate mode enables the count on a falling edge of TGATE and disables the count on the
rising edge of TGATE. This mode allows the timer to count conditionally, based on the state of
TGATE.
• The restart gate mode performs the same function as normal mode, except it also resets the counter
on the falling edge of TGATE.
This mode has applications in pulse interval measurement and bus monitoring as follows:
— Pulse measurement—The restart gate mode can measure a low pulse on TGATE. The rising
edge of TGATE completes the measurement and if TGATEn is connected externally to TINn,
it causes the timer to capture the count value and generate a rising-edge interrupt.
— Bus monitoring—The restart gate mode can detect a signal that is stuck abnormally low. The
bus signal should be connected to TGATE. The timer count is reset on the falling edge of the
bus signal and if the bus signal does not go high again within the number of user-defined
clocks, an interrupt can be generated.
The gate function is enabled in the GTMDR; the gate operating mode is selected in the GTCFRn.
TGATE is internally synchronized to the system clock. If TGATE meets the
asynchronous input setup time, the counter begins counting after one system
clock when working with the internal clock.
5.7.6.4 Cascaded Modes
GTCFRn[PCAS] and GTCFR2[SCAS] are used to put the timers into different cascaded modes:
• Non-cascaded mode (GTCFRn[PCAS] = 0 and GTGCF2[SCAS] = 0)
If GTCFRn[PCAS] = 0 and GTCFR2[SCAS] = 0, the each timer (timer 1, timer 2, timer 3, and
timer 4), function as a independent 16-bit timer with a 16-bit GTRFR, GTCPR, GTMDR, and
GTCNR for each one
GTRFR, GTCPR, and GTCNR should be referenced with appropriate 16-bit bus cycles.
GTRFR1, GTCPR1, GTCNR1
GTRFR3, GTCPR3, GTCNR3
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
(Figure 5-48). When working in the none-cascaded mode, the non-cascaded
Timer1
Capture
Timer3
Capture
Figure 5-48. Timers Non-Cascaded Mode Block Diagram
NOTE
Clock
Timer2
GTRFR2, GTCPR2, GTCNR2
Timer4
Clock
GTRFR4, GTCPR4, GTCNR4
System Configuration
Clock
Capture
Clock
Capture
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