Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 896

Enhanced Three-Speed Ethernet Controllers
threshold for that ring, flow control is asserted. Once enough BDs are freed for all active rings to meet
their respective free BD thresholds, application of back pressure cases.
Note: The eTSEC does not issue an exit pause frame (that is, pause frame with PTV of 0x0000) once all
active rings have sufficient BDs. Instead, it waits for the far-end pause timer to expire and start
re-transmission.
15.6.6 Hardware Assist for IEEE Std. 1588-CompatibleTimestamping
There is a push in industrial control applications to use Ethernet as the principal link layer for
communications. This requires Ethernet to be used for both data transfer and real-time control. For
real-time systems, each node is required to be synchronized to a master clock. The precision of this clock
is dictated by the application, but generally needs to be of the order of <1uSec for high-speed machinery
(for example, printing presses).
IEEE 1588 [1588] specifies a mechanism for synchronizing multiple nodes to a master clock. Support for
1588 can be done entirely in software running on a host CPU, but applications that require sub 10uSec
accuracy will need hardware support for accurate timestamping of incoming packets.
The eTSEC includes a new timer clock module to support the IEEE Std. 1588 timer standard. The
following sections describe the features, programming model, and implementation information.
15.6.6.1 Features
• 64-bit free running timer running from an external oscillator or internal clock
• Programmable timer oscillator clock selection
• Self-correcting precision timer with nano-second resolution
• Time stamp all incoming packets inline
– Maskable interrupts on received PTP packet's filer rule match
• Time stamp transmit packets when instructed in the TxFCB
– Maskable interrupts on transmit timestamp capture
• Two Tx timestamp registers per eTSEC with 16-bit tag for each of them to support burst mode.
• Time stamp capture on two general-purpose external triggers
– Maskable interrupts on GPIO timestamp trigger
– Programmable polarity of external trigger (GPIO) edge
• Two 64-bit alarm (future time) registers for future time comparison
– Maskable interrupts on alarm
• Three programmable timer output pulse period phase aligned with 1588 timer clock
– Maskable interrupts associated with each pulse
• Separate maskable timer interrupt event register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-178 Freescale Semiconductor