Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 978

Universal Serial Bus Interface
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
Status Transaction 0 Length
1
Status Transaction 1 Length
1
Status Transaction 2 Length
1
Status Transaction 3 Length
1
Status Transaction 4 Length
1
Status Transaction 5 Length
1
Status Transaction 6 Length
1
Status Transaction 7 Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Buffer Pointer (Page 5)
Buffer Pointer (Page 6)
1
Host controller read/write; all others read-only.
2
These fields may be modified by the host controller if the I/O field indicates an OUT.
16.5.3.1 Next Link Pointer
The first DWord of an iTD is a pointer to the next schedule data structure.
Bits Name
31–5 Link Pointer Correspond to memory address signals [31:5], respectively. This field points to another isochronous
transaction descriptor (iTD/siTD) or queue head (QH).
4–3 — Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Software should initialize this field to zero.
2–1 Typ Indicates to the host controller whether the item referenced is an iTD, siTD or a QH. This allows the host
controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
0 T Terminate
1 Link Pointer field is not valid.
0 Link Pointer field is valid.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-50
Next Link Pointer
1
1
1
1
1
1
1
1
Figure 16-38. Isochronous Transaction Descriptor (iTD)
Table 16-40. Next Schedule Element Pointer
15 14 13 12 11 10 9
2
ioc PG Transaction 0 Offset
2
ioc PG Transaction 1 Offset
2
ioc PG Transaction 2 Offset
2
ioc PG Transaction 3 Offset
2
ioc PG Transaction 4 Offset
2
ioc PG Transaction 5 Offset
2
ioc PG Transaction 6 Offset
2
ioc PG Transaction 7 Offset
EndPt
I/O
Description
8 7 6 5 4 3 2 1
00 Typ
2
2
2
2
2
2
2
2
R Device Address
Maximum Packet Size
Reserved Mult
Reserved
Reserved
Reserved
Reserved
Freescale Semiconductor
0 offset
T 0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C