Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 311

Bits Name
27–31 TTYPE Transfer type.
00000
00001
00010
00011
00100
00101
00110
00111
0100x
0101x
0110x
01110
6.2.7 Arbiter Event Address Register (AEADR)
Arbiter event address register (AEADR) reports the address of transaction that causes the error, which is
specified in the event register. See
AEADR is cleared only by power-on reset. The address of the first error event is stored. Note that this
means that AEADR does not change its value when AER is not clear. As AEADR is not effected by soft
or hard reset, software can read this register and determine the cause of the bus failure, even if the bus
failure had caused a deadlock situation. Refer to
information.
Figure 6-7 shows the fields of AEADR.
Offset 0x1C
0
R
W
Reset
Table 6-8 describes AEADR fields.
Bits Name
0–31 ADDR Address of the event reported in AEATR register. See
(AEATR),"
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 6-7. AEATR Field Descriptions (continued)
Address-only
Address-only
Single-beat or burst write
Reserved
Address-only
Reserved
Burst write
Reserved
Address-only
Single-beat or burst read
Address-only
Burst read
Section 6.2.3, "Arbiter Event Register (AER),"
Figure 6-7. Arbiter Event Address Register (AEADR)
Table 6-8. AEADR Field Descriptions
for more information.
Description
01111 Reserved
10000 Address-only
1XX01 Reserved
10010 Single-beat write
1XX11 Reserved
10100 ecowx—Illegal single-beat write
10110 Reserved
11000 Address-only
11010 Single-beat or burst read
11100 eciwx—Illegal single-beat read
11110 Burst read
Section 6.4.2, "Error Handling Sequence,"
ADDR
All zeros
Description
Section 6.2.6, "Arbiter Event Attributes Register
Arbiter and Bus Monitor
for more information.
for more
Access: User read/write
31
6-9