Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 345

• Memory control instructions—These instructions provide control of caches, TLBs, and segment
registers.
— Supervisor-level cache management instructions
— Translation lookaside buffer management instructions. Note that there are additional
implementation-specific instructions.
— User-level cache instructions
— Segment register manipulation instructions
• The e300 core implements the following instructions which are defined as optional by the
PowerPC architecture:
— Floating Select (fsel)
— Floating Reciprocal Estimate Single-Precision (fres)
— Floating Reciprocal Square Root Estimate (frsqrte)
— Store Floating-Point as Integer Word (stfiwx)
Note that this grouping of instructions does not indicate the execution unit that executes a particular
instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The
PowerPC architecture uses instructions that are 4 bytes long and word-aligned. It provides for byte,
half-word, and word operand loads and stores between memory and a set of 32 GPRs. It also provides for
word and double-word operand loads and stores between memory and a set of 32 FPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with distinct instructions.
The core follows the program flow when it is in the normal execution state. However, the flow of
instructions can be interrupted directly by the execution of an instruction or by an asynchronous event.
Either kind of interrupt may cause one of several components of the system software to be invoked.
7.3.2.2 Implementation-Specific Instruction Set
The e300 core instruction set is defined as follows:
• The core provides hardware support for all 32-bit PowerPC instructions.
• The core provides two implementation-specific instructions used for software table search
operations following TLB misses:
— Load Data TLB Entry (tlbld)
— Load Instruction TLB Entry (tlbli)
• The core implements the following instruction which is added to support critical interrupts (also
supported on the G2_LE). This is a supervisor-level, context synchronizing instruction.
— Return from Critical Interrupt (rfci)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
e300 Processor Core Overview
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