Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 923

Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
Set up the MII Mgmt for a read cycle to TBI's Control register (write the TBI's address and Register address),
Perform an MII Mgmt read cycle to verify state of TBI Control Register(0ptional)
(Uses the TBI address and Register address placed in MIIMADD register),
Set up the MII Mgmt for a write cycle to TBI's AN Advertisement register (write the PHY address and Register address),
The AN Advertisement register is at offset address 0x04 from the TBI's address. (in this case 0x10)
Write to MII Mgmt Control with 16-bit data intended for TBI's AN Advertisement register,
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half Duplex mode
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-176. RTBI Mode Register Initialization Steps
Set Soft_Reset,
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
Clear Soft_Reset,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2,
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
(I/F Mode = 2, Full Duplex = 1)
Initialize ECNTRL,
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
(This example has Statistics Enable = 1)
Initialize MAC Station Address,
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
to 02608C:876543, for example.
Initialize MAC Station Address,
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
to 02608C:876543, for example.
Assign a Physical address to the TBI,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
set to 16, for example.
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
The control register (CR) is at offset address 0x0 from TBIPA.
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
read the MIIMSTAT and look for AN Enable and other bit information.
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]
Perform an MII Mgmt write cycle to TBI.
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
Enhanced Three-Speed Ethernet Controllers
15-205