Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 924

Enhanced Three-Speed Ethernet Controllers
Table 15-176. RTBI Mode Register Initialization Steps (continued)
Set up the MII Mgmt for a write cycle to TBI's Control register (write the PHY address and Register address),
The control register (CR) is at offset address 0x00 from the TBI's address. (in this case 0x10)
Writing to MII Mgmt Control with 16-bit data intended for TBI's Control register,
This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
The PHY Status control register is at address 0x1 and in this case the PHY Address is 0x10.
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx'd)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00x_x110_0000]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-206
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
Perform an MII Mgmt write cycle to TBI.
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
Check to see if PHY has completed Auto-Negotiation.
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0001]
Perform an MII Mgmt read cycle of Status Register.
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
read the MIIMSTAT register and check bit 10 (AN Done)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
Perform an MII Mgmt read cycle of AN Expansion Register.
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
Clear IEVENT register,
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize IMASK (Optional)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize GADDR n (Optional)
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
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